Field
The present invention relates to nanowire devices. More particularly embodiments of the present invention relate to nanowire LED devices.
Background Information
Light emitting diodes (LEDs) are increasingly being considered as a replacement technology for existing light sources. For example, LEDs are found in signage, traffic signals, automotive tail lights, mobile electronics displays, and televisions. Various benefits of LEDs compared to traditional lighting sources may include increased efficiency, longer lifespan, variable emission spectra, and the ability to be integrated with various form factors.
Conventional planar-type semiconductor-based LEDs are generally patterned from layers grown across a wafer surface. More particularly, planar-type semiconductor-based LEDs include one or more semiconductor-based active layers sandwiched between thicker semiconductor-based cladding layers. More recently bottom-up approaches have been used to form nanowire LED structures that may offer several advantages to the planar-type LEDs, including lower dislocation density, greater light extraction efficiency, and a larger active region surface area relative to substrate surface area.
In one implementation illustrated in FIG. 1 a bulk LED substrate 100 includes a buffer layer 110 grown on a growth substrate 102. A patterned mask layer 112 (e.g. a nitride layer, such as silicon nitride masking layer) is then formed on a surface of the buffer layer 110 to define the bottom interface area for growth of the nanowire cores 114 using a suitable growth technique such as chemical beam epitaxy or vapor phase epitaxy. Thus, the bottom-up formation of each nanowire core 114 may be accomplished using the crystallographic orientation of the underlying buffer layer 110 without the required use of a particle or catalyst, and the width and pitch of the nanowire cores 116 can be defined by lithographic patterning of mask layer 112.
Epitaxial growth conditions for the nanowire cores may be controlled for vertical growth direction. Once the determined height is achieved, epitaxial growth conditions are changed to create a core-shell structure with the active layer 116 and doped shell 118 around the nanowire cores 114. Alternatively, nanowires can be formed using a similar technique using vertical growth conditions for the active layer and both cladding layers resulting in a sandwiched configuration similar to the planar-type LEDs rather than a core-shell structure.
Devices implementing arrays of nanowires are typically packaged in two manners. One includes leaving the array of nanowires on the original growth substrate such as described in U.S. Pat. No. 7,396,696 and U.S Publication No. 2011/0240959. In such implementations, the buffer layer functions as an electric current transporter layer to which a bottom electrode is formed, and a common top electrode is formed over the array of nanowires. Another implementation includes flip chip packaging the arrays of nanowires onto a receiving substrate using solder bumps then removing the growth substrate as described in U.S Publication Nos. 2011/0309382 and 2011/0254034.